Department: Electrical & Computer Engineering
Research Institute Affiliation: California Institute for Telecommunications and Information Technology (Calit2)
Faculty Advisor(s): James Buckwalter

Primary Student
Name: Mehmet Parlak
Email: mparlak@ucsd.edu
Phone: 858-534-5665
Grad Year: 2012

CMOS processes have made a profound impact on RF wireless communication and promise to also change communication at microwave and millimeter-wave bands. While much research interest has occurred at 60 GHz for short range communication, satellite communication at Ka, Ku, and Qbands holds promise for commercial applications. Realizing transmitters and receivers in silicon processes at these bands is challenging. For a Q-band uplink, several watts of transmit power are required to achieve a reasonable SNR. Satellite communication transceivers for high-capacity applications benefit from phased arrays since a highly directive antenna array improves the signal-to-noise ratio, hence channel capacity, significantly. Previously, mm-wave phased arrays at satellite bands have been demonstrated using SiGe and CMOS processes. Highly-scaled digital CMOS SOI is an excellent candidate platform for digital, analog and RF integration in a monolithic system-on-chip (SOC) package. Monolithic integration in CMOS SOI minimizes the system and packaging complexity, reduces system variability, and supports embedded RAM and microprocessors for radiation hard applications. However, the application of digital CMOS SOI technologies for RF applications requires a focus beyond the scaling and optimization of transistors. This poster presents the variety of efforts based on scaled CMOS SOI technology have shown low noise amplifiers, low loss mixers and SPDT switches implemented in a 45-nm CMOS SOI process. First, a double balanced passive I/Q mixer exhibits a conversion loss of 8.35 dB at 44 GHz and IIP3 of 15.5 dBm. At a fixed IF of 200 MHz, the minimum I/Q gain and phase imbalance is 0.25 dB and 1.9. Second, a single pole double throw (SPDT) switch demonstrates a measured insertion loss of less than 1.7 dB at 45 GHz and IIP3 of 18.2 dBm. Finally, a low noise amplifier (LNA) is designed with simultaneous noise and input power matching and shows a noise figure of 2.9 dB at 47 GHz. The output P1dB compression power is 3 dBm. The results demonstrate record performance for the mm-wave circuits in CMOS SOI; LNA, SPDT switch and passive mixer.

Related Files:

  1. Researchexpoposter_MehmetParlak1.pdf

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