119. QUANTIZED MIN-SUM DECODERS WITH LOW ERROR FLOOR FOR LDPC CODES

Department: Electrical & Computer Engineering
Research Institute Affiliation: Center for Magnetic Recording Research (CMRR)
Faculty Advisor(s): Paul Siegel

Primary Student
Name: Xiaojie Zhang
Email: xiz005@ucsd.edu
Phone: 858-534-3559
Grad Year: 2012

Abstract
The error floor phenomenon observed with LDPC codes and their graph-based, iterative, message-passing (MP) decoders is commonly attributed to the existence of error-prone substructures - variously referred to as near codewords, trapping sets, or absorbing sets - in a Tanner graph representation of the code. Many approaches have been proposed to lower the error floor by designing new LDPC codes with fewer such substructures or by modifying the decoding algorithm. In this paper, we show that the source of the error floors observed in the literature may be the message quantization rule used in the iterative decoder implementation. We then propose a new quantization method to overcome the limitations of standard quantization rules. Performance simulation results for two LDPC codes commonly found to have high error floors when used with the fixed-point min-sum decoder and its variants demonstrate the validity of our findings and the effectiveness of the proposed quantization algorithm.

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