100. MEMORY INTERFACE EXPLORATION WITH CACTI'S POWER-AREA-TIMING MODELS

Department: Electrical & Computer Engineering
Faculty Advisor(s): Andrew B. Kahng

Primary Student
Name: Vaishnav Srinivas
Email: vasriniv@ucsd.edu
Phone: 858-822-5003
Grad Year: 2014

Abstract
CACTI is an analytical memory modeling tool, which can calculate delay, power, area and cycle time for various memory technologies. For a given set of input parameters, the tool performs a detailed design space exploration across different array organizations and on-chip interconnects, and outputs a design that meets the input constraint. The memory interface is often a limiting factor in designing high-bandwidth, low-power memory accesses.This poster describes an extension to CACTI that includes off-chip interconnect, IO and PHY for the DRAM interface. It allows for a design space exploration framework within CACTI that includes models for the power, voltage and timing margins of the memory interface for various server and mobile configurations. This framework allows for tradeoffs between memory capacity, bandwidth and power of the memory interface. We present two case studies showing such tradeoffs on LRDIMM and 3-D memory configurations. The poster illustrates the following: (1) Models for power of the IO, PHY and interconnect for server and mobile configurations. (2) Models for voltage and timing margins based on sensitivity analysis for server and mobile configurations. (3) A framework to include these models into CACTI, thus enabling tradeoffs within the memory subsystem. (4) Two industry-driven case studies that use the models developed and provide insights into the tradeoffs between the configurations. The results show that LRDIMM and Buffer-on-Board designs offer ways to increase capacity at higher data-rates, while a 3-D hybrid memory cube offers significantly higher bandwidth than other configurations.

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