63. TRIMMED VLIW: MOVING APPLICATION SPECIFIC PROCESSORS TOWARDS HIGH LEVEL SYNTHESIS

Department: Computer Science & Engineering
Research Institute Affiliation: Graduate Program in Computational Science, Mathematics, and Engineering (CSME)
Faculty Advisor(s): Ryan Kastner

Primary Student
Name: Janarbek Matai
Email: jmatai@ucsd.edu
Phone: 858-405-2529
Grad Year: 2014

Abstract
We describe a synthesis methodology called Trimmed VLIW, which we argue lies between application specific processors and high level synthesis. Much like application specific processors, our methodology starts from a known instruction set architecture and customizes it to create the final implementation. However, our approach goes further as we not only add custom functional units and define the parameters of the register file, but we also remove unneeded interconnect, which results in a data path that looks more similar to that created by high level synthesis tools. We show that there are substantial opportunities for eliminating unused resources, which results in an architecture that has significantly smaller area. We compare area, delay and performance results of a base architecture with trimmed one. Preliminary results show by only trimming wires we have an average of 25\% area reduction while improving the performance around 5 %.

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