79. STACKED FET Q-BAND AMPLIFIER IN 45-NM CMOS WITH SATURATED OUTPUT POWER ABOVE 21 DBM

Department: Electrical & Computer Engineering
Research Institute Affiliation: Center for Wireless Communications (CWC)
Faculty Advisor(s): Peter M Asbeck | James Buckwalter | Larry Larson
Award(s): Honorable Mention

Primary Student
Name: Hayg-Taniel Dabag
Email: hdabag@ucsd.edu
Phone: 858-255-1551
Grad Year: 2013

Student Collaborators
Bassel Hanafi, bhanafi@ucsd.edu | Fatih Golcuk, fgolcuk@ucsd.edu

Abstract
A stacked FET, single-stage Q-band CMOS power amplifier (PA) is presented. The design uses series connection of four FETs to avoid breakdown to allow a high drain supply voltage, which in turn allows high output power and a broadband output matching network. The amplifier achieves a saturated output power above 21 dBm while achieving a maximum power-added-efficiency (PAE) above 20 % from 38 GHz to 47 GHz. On-chip shielded coplanar waveguide (CPW) transmission lines as well as metal finger capacitors were used for input and output matching. The IC was implemented in a 45-nm CMOS silicon-on-insulator (SOI) process. The chip occupies an area of 600um x 500um.

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