100. ILP-BASED CO-OPTIMIZATION OF CUT MASK LAYOUT, DUMMY FILL AND TIMING FOR SUB-14NM BEOL TECHNOLOGY

Department: Electrical & Computer Engineering
Faculty Advisor(s): Andrew B. Kahng

Primary Student
Name: Lutong Wang
Email: luw002@ucsd.edu
Phone: 858-822-5003
Grad Year: 2019

Student Collaborators
Kwangsoo Han, kwhan@ucsd.edu | Hyein Lee, hyeinlee@ucsd.edu

Abstract
Self-aligned multiple patterning (SAMP), due to its low overlay error, has emerged as the leading option for 1D gridded back-end-of-line (BEOL) in sub-14nm nodes. To form actual routing patterns from a uniform ?sea of wires?, a cut mask is needed for line-end cutting or realization of space between routing segments. Constraints on cut shapes and minimum cut spacing result in end-of-line (EOL) extensions and non-functional (i.e. dummy fill) patterns; the resulting capacitance and timing changes must be consistent with signoff performance analyses and their impacts should be minimized. In this work, we address the co-optimization of cut mask layout, dummy fill, and design timing for sub-14nm BEOL design. Our central contribution is an optimizer based on integer linear programming (ILP) to minimize the timing impact due to EOL extensions, considering (i) minimum cut spacing arising in sub-14nm nodes; (ii) cut assignment to different cut masks (color assignment); and (iii) the eligibility to merge two unit-size cuts into a bigger cut. We also propose a heuristic approach to remove dummy fills after the ILP-based optimization by extending the usage of cut masks. Our heuristic can improve critical path performance under minimum metal density and mask density constraints. In our experiments, we study the impact of number of cut masks, minimum cut spacing and metal density under various constraints. Our studies of optimized cut mask solutions in these varying contexts give new insight into the tradeoff of performance and cost that is afforded by cut mask patterning technology options.

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