Department: Electrical & Computer Engineering
Faculty Advisor(s): Andrew B. Kahng

Primary Student
Name: Hye In Lee
Email: hil001@ucsd.edu
Phone: 858-822-5003
Grad Year: 2017

Student Collaborators
Kwangsoo Han, kwhan@ucsd.edu

Technology scaling to 10nm and below introduces complex intra-row and inter-row constraints in standard-cell detailed placement. Examples of such constraints are found in rules for drain-drain abutment, minimum implant region area and width, oxide diffusion (OD) notching and jogging, etc. Typically, these rules are too complex for the normal global-detailed placement flow to fully consider. On the other hand, guardbanding the library cell design so that arbitrary cell placement adjacencies are all ?correct by construction? has increasingly high area cost. This motivates the introduction of a final legalization phase for standard-cell placement tools in advanced (particularly 10nm and 7nm) foundry nodes. In this work, we develop a mixed integer linear programming (MILP)-based placer, called DFPlacer, for final phase design rule violation (DRV) fixing. DFPlacer finds (near-) DRVfree solutions considering various complex layout constraints including minimum implant width, drain-drain abutment, and oxide diffusion jogs. To overcome the runtime limitation of MILP-based approaches, we implement a distributable optimization strategy based on partitioning of the block layout into windows of cells that can be independently legalized. Using layouts in an abstracted 7nm library, we find that DFPlacer fixes 99% of DRVs on average with minimal impacts on area and timing. We also study an area-DRV tradeoff between two types of standard-cell library strategies, namely, with and without dummy poly gates.

Industry Application Area(s)

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