71. HARDWARE ACCELERATED GRAPH ANALYTICS IN A RECONFIGURABLE SYSTEM

Department: Computer Science & Engineering
Faculty Advisor(s): Ryan Kastner

Primary Student
Name: Dajung Lee
Email: dal064@ucsd.edu
Phone: 858-999-4731
Grad Year: 2017

Abstract
In the era of Big Data, as cloud computers get more attentions, graph-represented algorithm or graph-based network analysis becomes a challenging problem. Many computer science researchers have been trying to accelerate graph based algorithm using various approaches in different abstraction level. However, because of its irregular structure and unpredictable data dependencies between nodes, researchers face difficulties to apply a conventional parallel approach to accelerate them. Most of issues are arose from accessing memory in an unpredictable way. In other words, transferring or communicating data without data locality is a critical issue. An FPGA has small, but many memory blocks capable of higher data bandwidth, and also can afford to achieve pipelining and parallel operations for very computation demanding applications. I would like to propose an asynchronous parallel graph processing architecture using an FPGA-CPU heterogeneous system based on massage passing interface to solve large scale graph analytics problems.

Industry Application Area(s)
Internet, Networking, Systems | Software, Analytics

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