73. MACHINE LEARNING FOR SYSTEM LEVEL DESIGN SPACE EXPLORATION ON FPGAS

Department: Computer Science & Engineering
Faculty Advisor(s): Ryan Kastner

Primary Student
Name: Pingfan Meng
Email: pmeng@ucsd.edu
Phone: 858-534-8908
Grad Year: 2016

Student Collaborators
Alric Althoff, aalthoff@ucsd.edu | Quentin Gautier, qkgautier@ucsd.edu

Abstract
FPGA Design Space Exploration (DSE) is a challenging task due to its time consuming tool chain, especially with modern high-level design tools such as OpenCL-to-FPGA. The design space for a typical OpenCL application contains thousands of possible designs even when considering a small number of design space parameters. Synthesizing all these possible designs could consume months of compute time. To address this issue, we present a machine learning framework that automatically explores the design space of the OpenCL designs on the FPGA. For the same prediction quality, our framework reduces the synthesis complexity by 1.6 − 2.89 (hundreds of synthesis hours) against the other state of the art frameworks for FPGA DSE.

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