73. MACHINE LEARNING FOR SYSTEM LEVEL DESIGN SPACE EXPLORATION ON FPGAS
Name: Pingfan Meng
Grad Year: 2016
FPGA Design Space Exploration (DSE) is a challenging task due to its time consuming tool chain, especially with modern high-level design tools such as OpenCL-to-FPGA. The design space for a typical OpenCL application contains thousands of possible designs even when considering a small number of design space parameters. Synthesizing all these possible designs could consume months of compute time. To address this issue, we present a machine learning framework that automatically explores the design space of the OpenCL designs on the FPGA. For the same prediction quality, our framework reduces the synthesis complexity by 1.6 − 2.89× (hundreds of synthesis hours) against the other state of the art frameworks for FPGA DSE.