UC San Diego Computer Engineering Students
Take Lead in Circuit Design Contest
San Diego, Calif., April 23, 2013 -- A team composed of students from the University of California, San Diego and the University of Michigan won more prize money than any other entry in the 2013 Discrete Gate Sizing Contest at the ACM International Symposium on Physical Design (ISPD).
The gate-sizing contest judged the teams in two categories. The “primary” category looked at circuit-power quality only; the “secondary” category looked at how well each entry did with the tradeoff between circuit-power quality and runtime optimization. (Runtime is the wall clock time from the beginning to the end of the execution of the submitted binary code program.)
The UC San Diego-Michigan’s Team Triton took first place in the “secondary” metric that encouraged contestants to strike the best tradeoff. The team also won cash for their second-place finish in the “primary” category. So while Team South Brazil, hailing from two Brazilian universities, edged them out for first place in the primary metric, the team from two Brazilian universities finished of the money in the secondary category. The overall result: Team Triton won the most cash. (For details on cash prizes and contest rules, visit the contest website.)
A team advised by Prof. Kahng, a professor in the departments of electrical and computer engineering and computer science at the Jacobs School of Engineering at UC San Diego, also won the very first ISPD contest in 2005.
The contest challenges teams from around the world to advance the state of the art in semiconductor design, first on faster circuits and more compact layouts. But in 2013, the focus was on discrete gate-sizing for lower-power operation. The contest was sponsored with support from Intel, Cadence, and Synopsys (which makes the industry-standard software that the contest used to evaluate circuit timing).
This year’s contest encouraged the use of smarter algorithms for circuits to use less power. “The goal of the contest was to develop a ‘near-industry-strength’ gate-sizing tool to achieve minimum leakage power while satisfying electrical and timing constraints,” said Kahng, who also is involved with Calit2's Qualcomm Institute. “They had to develop optimization algorithms for sizing, and an accurate timing estimator.”
“In advanced, 32-nanometer-and-below technology nodes, leakage power has become a top concern for designers of integrated circuits, because it has increased up to 50 percent of the total power consumption in integrated circuits,” said fifth-year Ph.D. student Seokhyeong Kang. “According to the semiconductor technology roadmap, power is – and has been – the number-one grand challenge for the entire semiconductor industry.”
“The main goal of gate sizing is to reduce leakage power, so it makes sense that this reduction is the primary metric in the ISPD contest,” added teammate Hyein Lee, a first-year electrical and computer engineering grad student. “However, in real-world design projects, the turnaround time that we call ‘runtime’ is also very critical, since it impacts the tapeout schedule and the number of cycles of design improvements.” [Tapeout refers to the final phase of the chip design cycle, when the artwork for the photomask of a circuit is sent for manufacture.]
It is that second metric that considers both leakage reduction and runtime, and in that category, Team Triton placed #1.
According to the UC San Diego team members, for the 2013 contest, they focused on the sizer implementation, including interconnect delay estimation, methods to fix timing violations, and better quality of power reduction. Their colleagues from the University of Michigan focused on improving the speed of the program by optimizing codes.
“Our starting point was a joint sizing approach that our UCSD-Michigan team published in 2012,” explained Lee, referring to “Sensitivity-guided metaheuristics for accurate discrete gate sizing,” a paper delivered at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2012). “The contest also allowed our team to invoke a ‘golden’ commercial tool in order to check the feasibility of solutions, so we used a fast socket interface between programs and exploited accurate timing analysis from the commercial tool during the design optimization.”
In addition, said teammate Seokhyeong Kang, “we also used a ‘go with the winners’ metaheuristic optimization strategy that could exploit the available multi-processor platform used by the contest organizers from Intel.”
Intel researchers substantially extended their infrastructure used for the ISPD 2012 contest, so as to evaluate both gate and interconnect delay, and checked capacitance and slew constraints (in addition to full-netlist timing constraints). Total runtime per benchmark was limited, with tighter limits in a secondary category, where tool runtime could be traded off for leakage power.
The UC San Diego-Michigan team applied a parallel search approach in their optimizer: the code was tuned to use up to 16 processor cores within the given runtime budget in order to find a high-quality solution as fast as possible. Indeed, the use of parallel computing was encouraged, and contestants were allowed to use up to 16 parallel hardware threads on evaluation servers at Intel.
Exploiting these computational resources, Team Trident’s optimization framework successfully handled circuits with 0.98 million gates during the final stage of the contest, as well as an internal timing analysis tool that erred by single picoseconds (on average) compared to the industry signoff timer.
The UC San Diego students note that the 2013 contest was substantially more difficult compared to the previous year’s competition. “This year’s contest became much more difficult because, unlike in 2012, interconnect wires between cells were considered,” said Lee. “This is a major reason why more than half of the original contestants did not pass the qualification for the final round, or they just dropped out.”
Twenty-five teams from eight different countries registered for the 2013 competition – more than half from Asia – but ultimately, only nine teams made it all the way to making final submissions.
When the winners were announced at ISPD 2013 in Lake Tahoe, Nevada, none of the UC San Diego members of Team Triton were there in person because of a scheduling conflict. They spent two months preparing for the contest, and submitted their binary-code program to the contest organizers, who provided the testbed on which all of the teams’ solutions were evaluated.
Although Team Trident seems like a natural moniker for a team from UC San Diego, Kang and Lee note that the trident is also a symbol for the Ukraine (where the Michigan adviser, Prof. Markov, is from). “Our sizer also finds a solution with multiple search paths, just as the trident has multiple points in the spear,” said Ph.D. student Seokhyeong Kang. “So everyone liked the name for different reasons!”
According to Prof. Kahng, the team also benefited from a long history of research that his group has pursued in the Jacobs School of Engineering. Leakage power reduction was the focus of Blaze DFM, a startup that he co-founded in 2004. His group has also maintained a Gate Sizing website since 2010, containing open-source optimization tools from researchers at UCLA and UC San Diego. “Having this past experience with industry designs and design flows helped provide intuition about how to attack the problem,” observed Kahng.
In addition to Team Triton and Team South Brazil, the top-five entries in the Gate Sizing Contest came from the Chinese University of Hong Kong, Northwestern University, and a joint entry by Japan’s Keio University and Taiwan’s National Chiao Tung University.
2013 ISPD Discrete Gate Sizing Contest »
ACM International Symposium on Physical Design »
EE Times Article on 2013 ISPD »
2013 ISPD Contest Summary Slides »
ICCAD 2012 Paper »
Jacobs School of Engineering »
More Computer Science and Engineering News Via RSS More Electrical and Computer Engineering News Via RSS