UCSD Jacobs School of Engineering University of California San Diego
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Battling ‘Shadow’ Moore’s Law

CSE professor Andrew B. Kahng, a pioneer in the semiconductor design-to-manufacturing interface, is keeping track of the costs of Moore's Law. He is the former chair of the international working group for design technology for the International Technology Roadmap for Semiconductors, a document that defines the next 15 years of technologies needed to double the density of transistors every two to three years to boost the speed and complexity of integrated circuits. Kahng says a "shadow Moore's Law," indicates that the cost incurred before "volume production" of the fastest, most complex integrated circuits is growing exponentially, creating a barrier to deployment of the latest semiconductor technology.

Kahng is using knowledge of chip designers' intent to solve "the problem of the $2 million mask set," a reference to the price of integrated circuit stencils. The size of mask features has become significantly smaller than the wavelength of light used to create them. "I'm trying to cut IC manufacturing costs by reducing the shape complexity of the stencil," says Kahng. Semiconductor companies have shown keen interest in a paper titled "Joining the Design and Mask Flows for Better and Cheaper Masks," which Kahng's research group presented at the September 2004 BACUS Symposium on Photomask Technology and Management.