124. emerging vertical nanowirefet technology for energy efficient computing

Department: Electrical & Computer Engineering
Research Institute Affiliation: Graduate Program in Computational Science, Mathematics, and Engineering (CSME)
Faculty Advisor(s): Tajana S. Rosing

Primary Student
Name: Joonseop Sim
Email: j7sim@ucsd.edu
Phone: 858-775-3004
Grad Year: 2019

Vertical Nanowire-FET(VNFET) is a promisingcandidate to succeed in industry mainstream due to its superiorsuppression of short-channel-effects and area efficiency. However,to design logic gates, CMOS is not an appropriate solutiondue to the process incompatibility with VNFET, which createsa technical challenge for mass production. In this work, wepropose a novel VNFET-based logic design, calledVnanoCML(Vertical Nanowire Transistor-based Current Mode Logic), whichaddresses the process issue while significantly improving powerand performance of diverse logic designs. Unlike the CMOS-based logic, our design exploits current mode logic to overcomethe fabrication issue. Furthermore, we reduce drain-to-sourceresistance ofVnanoCML, which results in higher performanceimprovement without compromising the subthreshold swing. Inorder to show the impact of the proposedVnanoCML, wepresent two key logic designs, SRAM and full adder, and alsoevaluate the application-level effectiveness of digital designs forimage processing and mathematical computation. Our proposeddesign improves the fundamental circuit characteristics includingsensing margin, delay time and power consumption comparedto conventional planar MOSFET-based (PFET) circuits. Forexample, the circuit-level results show thatVnanoCMLcanenhance the performance and power by 45.6ืand 1.16ื,respectively. Furthermore, for the four ASICs designs, we showthatVnanoCMLimproves the energy-delay product by 38.5ืon average compared to PFET-based designs

Industry Application Area(s)
Electronics/Photonics | Semiconductor

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