87. information flow tracking for provably secure hardware design

Department: Computer Science & Engineering
Research Institute Affiliation: Graduate Program in Computational Science, Mathematics, and Engineering (CSME)
Faculty Advisor(s): Ryan Kastner

Primary Student
Name: Armaiti Ardeshiricham
Email: aardeshi@ucsd.edu
Phone: 858-281-3776
Grad Year: 2019

Abstract
Information Flow Tracking (IFT) provides a formal methodology for modeling and reasoning about security proper- ties related to integrity, confidentiality, and logical side channel. Recently, IFT has been employed for secure hardware design and verification. However, existing hardware IFT techniques either require designers to rewrite their hardware specifications in a new language or do not scale to large designs due to a low level of abstraction. In this work, we propose Register Transfer Level IFT (RTLIFT), which enables verification of security properties in an early design phase, at a higher level of abstraction, and directly on RTL code. The proposed method enables a precise understanding of all logical flows through RTL design and allows various tradeoffs in IFT precision. We show that RTLIFT achieves over 5 speedup in verification performance as compared to gate level IFT while minimizing the required effort for the designer to verify security properties on RTL designs.

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