89. surprise: a probabilistic metric of hardware design space complexity
Name: Alric Joseph Althoff
Grad Year: 2019
Designing computer hardware is difficult and time-consuming. This is true in part because of issues at the programming language level. High-level synthesis (HLS) tools aim to alleviate some of these difficulties by allowing software engineers to develop hardware using higher-level languages, like C/C++ and OpenCL instead of hardware design languages. Unfortunately, there is a gap between the paradigms and necessities of hardware development and the semantics of these high-level languages. The current generation of HLS design tools give developers access to these lower-level necessities through annotations in the source code. However, software engineers who aren't familiar with hardware design have difficulty efficiently finding the optimal combination of these annotations. This is a human and computational resource problem because each compilation and test of the hardware design can take several hours to complete. To address this loss of efficiency, several machine learning techniques have been published that automatically determine the optimal parameters for hardware cores written using HLS. None of these techniques terminate in a predictable amount of time, and they could run for days or weeks. To address this, we propose a novel spatial statistic to evaluate a small number of design samples and output a relative time frame for optimization to complete. We experimentally demonstrate that our statistic predicts the convergence rate of a state-of-the-art machine learning algorithm for automated design space exploration. These results show that integration of our statistic into the automated HLS design flow will allow more efficient scheduling of HLS software compilation resources and provide better estimates of project completion times.
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