115. vertical m1 routing-aware detailed placement for congestion and wirelength reduction in sub-10nm nodes

Department: Electrical & Computer Engineering
Faculty Advisor(s): Andrew B. Kahng

Primary Student
Name: Lutong Wang
Email: luw002@ucsd.edu
Phone: 858-822-5003
Grad Year: 2018

Student Collaborators
Kwangsoo Han, kwhan@ucsd.edu | Hyein Lee, hyeinlee@ucsd.edu

Abstract
Aggressive pitch scaling in sub-10nm manufacturing technology nodes has led to complex design rules which are extremely challenging for IC place-and-route tools. Standard-cell architectures have also undergone radical changes in order to best comply with the new design rules. For example, metal layers below the Metal-1 (M1) layer are used to gain additional routing resources. In this work, we study new cell architectures wherein inter-row M1 routing is allowed. Notably, the inter-row routing forces consideration of vertical alignment of cells. We propose a mixed-integer linear programming (MILP)-based, detailed placement optimization to maximize M1 routing utilization, which in turn reduces routing congestion and wirelength. Our optimization achieves 4X increase in vertical M1 routing, and up to 6.4% total routed wirelength reduction, with no adverse timing impact.

Industry Application Area(s)
Semiconductor

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