113. optimum logic synthesis constraints for ic physical implementation

Department: Electrical & Computer Engineering
Faculty Advisor(s): Andrew B. Kahng

Primary Student
Name: Tushar Shah
Email: t6shah@ucsd.edu
Phone: 858-822-5003
Grad Year: 2018

Low-power IC designs, particularly for mobile and IoT applications, must achieve functional correctness at multiple, widely differing performance targets, or ?modes?. For example, a given chip must function in a high-performance ?turbo? mode with elevated supply voltage, and at a low-performance ?voltage-scaled? mode with lowered supply voltage. Achieving a correct design without wasting area and power resources is increasingly challenging in advanced technology nodes. In this context, results from the logic synthesis step of IC implementation can strongly constrain what can be achieved in the subsequent physical design (?place-and-route?) steps. For modern systems-on-chip, traditional approaches to selecting a performance target for logic synthesis no longer lead to high-quality outcomes after placement and routing. We describe a methodology to accurately identify the synthesis corner that gives us optimum post-place and route results, while enabling satisfaction of timing constraints at given multiple modes and corners. Experiments are run using 28nm FDSOI libraries characterized at different body biases and supply voltages.

Industry Application Area(s)
Electronics/Photonics | Semiconductor

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