114. a pathfinding tool for 3d vlsi technology and design

Department: Electrical & Computer Engineering
Faculty Advisor(s): Andrew B. Kahng | Andrew Kahng
Award(s): Department Best Poster

Primary Student
Name: Ahmed Taha Elthakeb Youssef
Email: a1yousse@ucsd.edu
Phone: 858-247-9539
Grad Year: 2020

3D VLSI (3DV) offers a promising approach for continuation of Moore?s-Law value scaling in semiconductor-based products. 3DV enables wirelength reductions that lead to improved speed, power and integration density. It also enables the cost-effective heterogeneous integration of multiple technologies that is anticipated for future mobile and IoT applications. However, the benefits of 3DV are difficult to quantify across the myriad process, device and integration technology options that are available in the coming years. In this poster, we study what is arguably the most critical aspect of 3DV enablement: design methods for power delivery networks (PDNs). We first taxonomize 3DV PDN configurations that enable greater tunability of power, performance, area and cost tradeoffs in 3DV. We then describe a 3DV PDN ?pathfinding? tool that helps designers visualize tradeoffs across (i) number of stackable tiers; (ii) total design current; (iii) process and integration technology parameters, and (iv) system partitioning choices. Our results can contribute to more efficient and effective design space exploration for 3DV.

Industry Application Area(s)
Electronics/Photonics | Semiconductor | Software, Analytics

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