92. monolithic heterogeneously integrated high-power vertical-channel gan devices with si cmos electronics

Department: Electrical & Computer Engineering
Faculty Advisor(s): Shadi A. Dayeh

Primary Student
Name: Woojin Choi
Email: woc015@ucsd.edu
Phone: 858-750-5208
Grad Year: 2020

The way we communicate, store and access information, and the vehicles we use to transport are increasingly dependent on electric power conversion. In these and other applications, power density, switching frequency, light weight, and low cost are essential considerations to realize compact and efficient power conversion circuits. Si power devices dominated the market for several decades but their poor power conversion and switching efficiency are the major component of electric power losses in the generation, transmission and utility of electric power. Fundamentally new approaches that combine innovations at all levels of materials, devices, and circuits are necessary. The larger bandgap GaN has higher breakdown field, higher electron mobility and saturation velocity and lower dynamic on-resistance and lateral GaN HEMT devices started to penetrate the intermediate (600V) power device market. But the conduction of high current in thin surface layers of HEMTs has been known to yield heating, early breakdown, and reliability issues. Volume conduction in vertical GaN devices is expected to mitigate these issues and to increase the power density per unit area reducing the cost to become comparable to Si power devices yet with significantly better performance. But such devices require thick GaN layers, which on a cheap substrate such as Si, has never been attained before due to well known thermal mismatch between GaN and Si. Our group has overcome this barrier and we realized vertical GaN transistors in GaN layers monolithically grown on a Si substrate. In the context of power converters, this integration eliminates the chip-to-chip parasitic inductances and improve their overall power conversion efficiency. We propose here to utilize our new epitaxy techniques to demonstrate high-power vertical GaN transistors and to co-integrate them with Si CMOS on the same die to demonstrate a compact monolithically integrated power converter. We have successfully demonstrated selective area growth (SAG) approaches on patterns that are designed specifically to provide compliance to thermal mismatch stresses during the growth of thick crack-free GaN layers on Si. The resulting material quality and vertical trench-gate MISFET characteristics are comparable to that grown on synthetic GaN substrates (2? wafer costs $2600, >100 times more expensive than Si substrates). State of the art approaches to develop GaN devices with Si CMOS include wafer bonding or lateral device fabrication for over a decade, but there is no report to date on functional high power GaN transistors with Si CMOS gate drive circuits on a same substrate. This strongly suggests that a new approach is required. Our proposed project encompasses innovations at the materials, devices, and integration levels, because nobody else has succeeded in demonstration of high performance GaN devices and its monolithic integration through a bottom-up approach. We already showed possibilities of high performance GaN transistors through SAG epitaxy, so the next step of our project will make big impacts on the paradigm of the heterogeneous integration of GaN devices with Si CMOS for next generation compact high-power converters.

Industry Application Area(s)
Electronics/Photonics | Energy/Clean technology | Semiconductor

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