wireless powering of mm-scale fully-on-chip neural interfaces
Name: Jiwoong Park
Grad Year: 2018
This work presents guidelines for the design and optimization of on-chip coils used for wirelessly-powered mm-scale neural implants. Since available real estate is limited, on-chip coil design involves managing difficult trade-offs between the number of turns, trace width and spacing, proximity to other active circuits and metalization, quality factor, matching network performance/size, and load impedance conditions, all towards achieving high power transfer efficiency. To illustrate the design optimization procedure, a 3 mm x 3 mm on-chip coil is designed, and measurement results reveal a 3.82% power transfer efficiency for a 1.6 kOhm load that mimics a 100 uW neural interface.
Industry Application Area(s)
Electronics/Photonics | Life Sciences/Medical Devices & Instruments