COVID-19 Updates

Information is available for the campus community on the Return to Learn website. Please get vaccinated and stay up to date with County and State guidelines as well as CDC recommendations.

Faculty Profile

Tzu-Chien Hsueh

Asst Professor, Electrical and Computer Engineering

Analog and mixed-signal integrated circuits for wireline communication systems, data centers, Ethernet, electrical-to-optical interfaces, silicon photonics, data links, transceivers, serializers-deserializers (SerDes), and clock-and-data recovery (CDR).

Tzu-Chien Hsueh leads the Integrated Communication Circuits Lab at UC San Diego. The primary research objective is to develop analog and mixed-signal integrated circuits in advanced CMOS, monolithic, and heterogeneous process technologies for the broadband applications of high-speed low-power communication systems, data centers, Ethernet, and cloud computing networks. The lab's major circuit research topics include wireline electrical/optical transceiver analog front-ends, channel equalizations, clock-and-data recovery, clock distributions, data-conversion circuits, silicon photonics, on-chip performance analyzers, switch-capacitor filters, audio-band transceivers, and digital/mixed signal processing techniques. Hsueh's research philosophy emphasizes practical design innovations, solid theoretical analyses, coherent system performances, and robust circuit implementations.

Capsule Bio:

Tzu-Chien Hsueh joined the Electrical and Computer Engineering faculty at UC San Diego in 2018 as an Assistant Professor. He received his B.S. and M.S. degrees in Electrical Engineering from National Taiwan University, Taiwan, in 1999 and 2001, respectively; he received his Ph.D. degree in Electrical and Computer Engineering from the University of California, Los Angeles (UCLA) in 2010. From 2001 to 2006, Hsueh was a senior mixed-signal circuit design engineer in Hsinchu, Taiwan; he was working on high-performance audio-band transceivers and Gigabit Ethernet I/O communication systems. From 2010 to 2018, Hsueh was successively a Senior Research Scientist in Intel Lab Signaling Research and Senior Analog Engineer in Intel I/O Circuit Technology, Hillsboro, Oregon. He was the technical lead of the multiple Intel high-speed wireline communication research projects, including 200Gb/s SerDes Links, 7nm CMOS low-power Memory I/Os, ADC-DSP based receivers, and USB Type-C converged I/O transmitters.

In recognition of Hsueh’s industry experiences, he has been invited to serve on the Patent Committee of Intel Intellectual Property (Intel IP) and the Technical Committee of Intel Design & Test Technology Conference (DTTC). Currently, he serves on the Technical Program Committee of IEEE Custom Integrated Circuits Conference (CICC) and the mentoring program of IEEE Solid-State Society (SSCS). Hsueh received multiple Intel Division and Academy awards from 2012 to 2018, and he is a recipient of the IEEE 2015 Journal of Solid-State Circuits (JSSC) Best Paper Award.

Selected Publications:

Google Scholar Publications


Office Phone:

Jacobs School Faculty Update Your Profile