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Tzu-Chien Hsueh

Associate Professor, Electrical and Computer Engineering


Analog and mixed-signal integrated circuits for wireline communication systems, data centers, Ethernet, electrical-optical interfaces, silicon photonics, heterogeneous integrations, high-speed data links, transceivers, serializers-deserializers (SerDes), and clock-and-data recovery (CDR).

Tzu-Chien Hsueh leads the Integrated Communication Circuits Lab (ICCL) at the University of California San Diego (UC San Diego). The primary research objective is to develop analog and mixed-signal integrated circuits utilizing advanced CMOS, silicon photonics, and heterogeneously integrated process technologies for broadband data communications and computations in data centers, in-package chiplets, wafer-scale AI computing systems, and 5G/6G wireless radio-unit networks. The major circuit research topics include wireline electrical transceiver analog front-ends, optical modulators, silicon-photonics interposers, channel equalization, SerDes, CDR, clock distribution, data conversion circuits, on-chip performance analyzers, switch-capacitor filters, and digital/mixed-signal processing techniques. The research philosophy emphasizes practical design innovations, solid theoretical analyses, coherent system performances, and robust circuit implementations.

Capsule Bio:

Since 2018, Dr. Hsueh has been a faculty member and is currently an Associate Professor in the Department of Electrical and Computer Engineering at the University of California San Diego (UC San Diego). He received the B.S. and M.S. degrees in Electrical Engineering from National Taiwan University in 1999 and 2001, respectively, and received the Ph.D. degree in Electrical and Computer Engineering from the University of California, Los Angeles (UCLA), in 2010. From 2001 to 2006, Dr. Hsueh was a senior mixed-signal circuit design engineer in Hsinchu, Taiwan, where he worked on high-performance audio-band transceivers and Gigabit Ethernet I/O communication systems. From 2010 to 2018, Dr. Hsueh was successively a Senior Research Scientist in Intel Lab Signaling Research and a Senior Analog Engineer in Intel I/O Circuit Technology, Hillsboro, Oregon. He was the technical lead of multiple Intel high-speed wireline communication research projects, including 200-Gb/s SerDes Links, 7-nm CMOS low-power Memory I/Os, ADC-DSP-based receivers, and USB Type-C converged I/O transmitters.

In recognition of Dr. Hsueh’s industry experience, he has been invited to serve on the Patent Committee of Intel Intellectual Property (Intel IP) and the Technical Committee of Intel Design & Test Technology Conference (DTTC). From 2018 to 2024, he served on the Technical Program Committee of the IEEE Custom Integrated Circuits Conference (CICC), the mentoring program of the IEEE Solid-State Circuits Society (SSCS), and as a Guest Associate Editor for IEEE Solid-State Circuits Letters (SSC-L). Dr. Hsueh was a recipient of multiple Intel Division and Academy Awards from 2012 to 2018, the 2015 IEEE Journal of Solid-State Circuits (JSSC) Best Paper Award, the 2020 NSF CAREER Award, and the 2022 UC San Diego Best Teacher Award.

Selected Publications:

Google Scholar Publications


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Email:
tzhsueh@ucsd.edu

Office Phone:
858-534-4253