Faculty Profiles

Thanks to Moore's Law and emerging nanotechnology, we will soon be able to integrate multi-billion transistors on a single chip. For broadband communications applications such as high-speed switching and wireless communications, gigascale integration enables a new generation of VLSI architectures and circuit techniques. A major focus of Professor Lin's work is efficient implementations of switching, protocol processing, and signal processing algorithms in silicon. These sophisticated algorithms typically have enormous computational needs that can only be satisfied with specialized, highly parallel, pipelined architectures. Programmability is a key requirement in these architectures to cope with multiple incompatible standards and evolving protocols often found in communications applications. However, programmability and high-performance are often conflicting objectives. For wireless applications, the design problem is further complicated by the need for low power consumption to support battery constrained mobile applications. Lin's current research effort aims to tackle the conflicting objectives of programmability, high-performance, and energy efficiency. Lin is also an expert on design methodologies and design tools. His research effort also explores new ways to design modern VLSI systems in the gigascale era.

Capsule Bio:

Bill Lin joined the UC San Diego faculty in 1997. He received his Ph.D. in Electrical Engineering and Computer Science from the University of California, Berkeley. Prior to joining UC San Diego, Lin led the System Control and Communications Group at IMEC, Europe's largest independent microelectronics and information technology research center. At IMEC, he led a research team that worked on VLSI architecture, system design, and circuit techniques for system-on-chip applications. He has also previously held positions at Hewlett Packard, Hughes Electronics, and Western Digital. He multiple patents, nearly 200 journal and conference publications, and his awards include the 1995 best-paper award from IEEE Transactions on VLSI Systems.